1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more specifically to output driver devices.
2. Description of the Prior Art
As is well known, a phenomenon known as power supply line noise inductance effects can significantly decrease the potential output performance of an integrated circuit device. This phenomena, which results from the inductance on various signal lines both on chip and from chip to package, is proportional to both the inductance and to the rate of change of the current with respect to time (di/dt), and causes the output signal and the power supply lines to oscillate or bounce.
Since the output of the chip is not output until the power supply lines have settled down, the power supply line noise inductance has the effect of slowing down the potential output performance of an integrated circuit device. Many different design techniques have been developed in an attempt to limit di/dt and simultaneously increase the output performance of the chip.
A common approach to this problem is to limit the di/dt for all output drivers. Limiting di/dt both allows the power supply line to stabilize faster and increases the amount of time taken by an output driver to change states. However, with appropriate di/dt limiting, this tradeoff can still result in a decrease in the access time at the output pins of the integrated circuit package, which is an increase in device performance.
Limiting di/dt has been accomplished by several methods. One method is to add resistors to the power supply lines of the output transistors or the stage driving the output transistors. The resistors uniformly reduce the rate of switching of the output drivers. Another method to limit di/dt is to use an output driver designed to drive the load with a constant di/dt. Another approach is to provide power buses for the output drivers which are separate from the rest of the circuit.
It is known that the outputs at the output pins of the integrated circuit package do not all change state at the same time. Since the chip cannot be validly accessed until the slowest output pin is ready, a wait time exists between the time at which the fastest output pin changes state and the time at which the slowest output pin changes state.
Currently available methods for di/dt limiting increase device operating speed by minimizing power supply oscillations, but the methods do not attempt to reduce the wait time. Thus, overall device operating speed is less than the theoretical maximum speed.
It would be desirable to increase device operating speed beyond that currently achievable through the reduction of the power supply oscillation settling time without suffering wait time delays to the extent of the prior art.